Design Verification Engineer (SystemVerilog & UVM)

About the job
Job Title: Design Verification Engineer (SystemVerilog & UVM)

Location: Markham, ON, Canada (Onsite)

Time Zone: EST

Experience: 7–13 Years

Job Summary:

We are seeking an experienced Design Verification (DV) Engineer with strong expertise in SystemVerilog (SV) and UVM for onsite work in Markham, Canada. The ideal candidate will be responsible for verifying complex display IPs used in graphics cards, ensuring high-quality and performance standards through robust verification methodologies.

Key Responsibilities:

Perform functional verification of display IPs used in graphics processing units (GPUs).
Develop and execute IP, subsystem (SS), and end-to-end test plans.
Design and implement testbenches using SystemVerilog and UVM.
Create reusable verification components, environments, and test cases.
Perform debugging, root cause analysis, and issue resolution.
Collaborate with design and architecture teams to understand specifications and ensure coverage.
Ensure thorough coverage (code & functional) and regression testing.
Participate in verification planning, reviews, and documentation.
Required Skills & Qualifications:

7–13 years of experience in Design Verification.
Strong expertise in:
SystemVerilog (SV)
UVM (Universal Verification Methodology)
Hands-on experience with DV flow including testbench development, simulation, and debugging.
Experience in IP/Subsystem level and end-to-end verification.
Solid understanding of digital design fundamentals.
Experience with display IP verification or graphics-related domains is highly preferred.
Strong debugging and analytical skills.
Preferred Qualifications:

Prior experience working with graphics card or GPU-related IPs.
Familiarity with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor).
Experience working in a high-performance semiconductor environment